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PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232CABB, EDS1232CATA (4M words x 32 bits)
Description
The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words x 32 bits x 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86-pin plastic TSOP (II).
Features
* * * * * 2.5V power supply Clock frequency: 133MHz (max.) Single pulsed /RAS x32 organization 4 banks can operate simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length (BL): 1, 2, 4, 8 and full page * 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8) Interleave (BL = 1, 2, 4, 8) * Programmable /CAS latency (CL): 2, 3 * Byte control by DQM * Refresh cycles: 4096 refresh cycles/64ms * 2 variations of refresh Auto refresh Self refresh * FBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0247E40 (Ver. 4.0) Date Published July 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002
EDS1232CABB, EDS1232CATA
Ordering Information
Part number EDS1232CABB-75-E EDS1232CABB-1A-E EDS1232CABB-75L-E EDS1232CABB-1AL-E EDS1232CATA-75 EDS1232CATA-1A EDS1232CATA-75L EDS1232CATA-1AL 2.5V 4M x 32 4 Supply voltage 2.5V Organization (words x bits) Internal Banks 4M x 32 4 Clock frequency MHz (max.) 133 100 133 100 133 100 133 100 /CAS latency 3 2, 3 3 2, 3 3 2, 3 3 2, 3 86-pin plastic TSOP (II) Package 90-ball FBGA
Part Number
E D S 12 32 C A BB - 75 L - E
Elpida Memory Lead Free Type
D: Monolithic Device
Product Code S: SDRAM Density / Bank 12: 128M/4 Banks Bit Organization 32: x32 Voltage, Interface C: 2.5V, LVTTL Die Revision
Power Consumption Blank: Normal L: Low Power
Speed 75: 133MHz/CL3 100MHz/CL2 1A: 100MHz/CL2,3 Package TA: TSOP (II) BB: FBGA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
1 2 3 4 5 6 7 8 9
86-pin TSOP VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS A11 BA0 BA1 A10(AP) A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 (Top view) 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
A
DQ26 DQ24 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 DQ16 VSSQ DQM2 VDD A0 BA1 /CS A1 A11 /RAS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC A3 A6 NC A9 NC VSS
F
VSS DQM3
G
A4 A5 A8 CKE NC
H
A7
J
CLK
K
DQM1 /WE DQM0 DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ
L
VDDQ DQ8
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 VDD DQ0 DQ2
R
DQ13 DQ15 VSS
(Top view)
Pin name A0 to A11 BA0, BA1 DQ0 to DQ31 CLK CKE /CS /RAS /CAS /WE DQM0 to DQM3 VDD VSS VDDQ VSSQ NC
Function Address inputs Bank select Data input/output Clock input Clock enable Chip select Row address strobe Column address strobe Write enable DQ mask enable Supply voltage Ground Supply voltage for DQ Ground for DQ No connection
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
CONTENTS Description .................................................................................................................................................... 1 Features ........................................................................................................................................................ 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Pin Configurations......................................................................................................................................... 3 Electrical Specifications ................................................................................................................................ 5 Block Diagram............................................................................................................................................. 10 Pin Function ................................................................................................................................................ 11 Command Operation................................................................................................................................... 12 Truth Table.................................................................................................................................................. 16 Simplified State Diagram ............................................................................................................................ 22 Programming Mode Registers .................................................................................................................... 23 Mode Register............................................................................................................................................. 24 Power-up sequence .................................................................................................................................... 27 Operation of the SDRAM ............................................................................................................................ 28 Timing Waveforms ...................................................................................................................................... 44 Package Drawing........................................................................................................................................ 51 Recommended Soldering Conditions ......................................................................................................... 53 Revision History .......................................................................................................................................... 56
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up (refer to the Power up sequence). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD, VDDQ IOS PD TA Tstg Rating -0.5 to +3.6 -0.5 to +3.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (TA = 0 to +70C)
Parameter Symbol min. typ. max. Unit Notes
Supply voltage
Input high voltage Input low voltage
VDD, VDDQ
VSS VIH VIL
2.3
0 1.7 -0.3
2.5
0
2.7
0 VDD + 0.3* 0.7
1
V
V V V
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width 5ns). 2. VIL (min.) = -1.5V (pulse width 5ns).
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
DC Characteristics (TA = 0 to +70C, VDD, VDDQ = 2.5V0.2V, VSS, VSSQ = 0V)
Parameter /CAS latency Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current Refresh current Self refresh current Self refresh current (L-version) Symbol IDD1 IDD1 IDD2P IDD2PS Grade -75 -1A -75 -1A max. 105 100 105 100 1 1 Unit mA mA mA mA Test condition Burst length = 1 tRC tRC (min.) IO = 0mA One bank active CKE VIL (max.) tCK = 15ns CKE VIL (max.) tCK = CKE VIH (min.) tCK = 15ns CS VIH (min.) Input signals are changed one time during 30ns CKE VIH (min.) tCK = CKE VIL (max.) tCK = 15ns CKE VIL (max.), tCK = CKE VIH (min.), tCK = 15 ns, /CS VIH (min.), Input signals are changed one time during 30ns. CKE VIH (min.), tCK = , tCK tCK (min.), IO = 0mA, All banks active tRC tRC (min.) VIH VDD - 0.2V, VIL GND + 0.2V 2 3 Notes 1
IDD2N
20
mA
IDD2NS IDD3P IDD3PS
8 5 4
mA mA mA
IDD3N
25
mA
IDD3NS IDD4 IDD5 IDD6 IDD6 -xxL -75 -1A -75 -1A
15 150 130 210 200 2.0 0.6
mA mA mA mA mA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.). 2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.). 3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). DC Characteristics 2 (TA = 0 to +70C, VDD, VDDQ = 2.5V0.2V, VSS, VSSQ = 0V)
Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL min. -1.0 -1.5 2.0 -- max. 1.0 1.5 -- 0.4 Unit A A V V Test condition 0 = VIN = VDDQ, VDDQ = VDD, All other pins not under test = 0V 0 = VIN = VDDQ DOUT is disabled IOH = -1mA IOL = 1mA Notes
Output high voltage Output low voltage
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Pin Capacitance (TA = 25C, f = 1MHz)
90-ball FBGA Parameter Input capacitance Symbol Pins CI1 CI2 Data input/output capacitance CI/O Address min. 1.5 Typ -- -- -- max. 3.0 3.0 5.5 86-pin TSOP (II) min. 2.5 2.5 4.0 Typ -- -- -- max. 4.0 4.0 6.5 Unit pF pF pF Notes
CLK, CKE, /CS, /RAS, 1.5 /CAS, /WE, DQM DQ 3.0
AC Characteristics (TA = 0 to +70C, VDD, VDDQ = 2.5V0.2V, VSS, VSSQ = 0V)
-75 Parameter System clock cycle time (CL = 2) (CL = 3) CLK high pulse width CLK low pulse width Access time from CLK Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance Input setup time Input hold time CKE setup time (Power down exit) ACT to REF/ACT command period (operation) (refresh) Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Last data into active latency Symbol tCK tCK tCH tCL tAC tOH tLZ tHZ tSI tHI tCKSP tRC tRC tRAS tRCD tRP tDPL tDAL min. 10 7.5 2.5 2.5 -- 2 0 2 1.5 0.8 1.5 67.5 67.5 45 20 20 15 2CLK + 20ns 15 2 0.5 -- max. -- -- -- -- 5.4 -- -- 5.4 -- -- -- 120000 30 64 -1A min. 10 10 3 3 -- 2 0 2 2 1 2 70 70 50 20 20 20 2CLK + 20ns 20 2 0.5 -- max. -- -- -- -- 6 -- -- 6 -- -- -- 120000 -- -- 30 64 ns CLK ns ms Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes
Active (a) to Active (b) command period tRRD Mode register set cycle time Transition time (rise and fall) Refresh period (4096 refresh cycles) tRSC tT tREF
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Test Conditions * AC high level input voltage / low level input voltage: 2.1V / 0.3V * Input timing measurement reference level: 1.2V * Transition time (Input rise and fall time): 1ns * Output timing measurement reference level: 1.2V * Termination voltage (Vtt): 1.2V
tCK tCH CLK 2.1V 1.2V 0.3V tSETUP tHOLD 2.1V 1.2V 0.3V tAC tOH Output tCL
Input
Vtt Z = 50 Output 30pF 50
Input Waveforms and Output Load
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CL = 2) (CL = 3) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CL = 2) (CL = 3) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command /CS to command disable Power down exit to command input Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lDAL lSEC lHZP lHZP lAPR lEP lEP lCCD lWCD lDID lDOD lCLE lMRD lCDD lPEC -75 133 7.5 3 9 6 3 2 2 1 5 9 3 1 -2 1 0 0 2 1 2 0 1 100 10 2 7 5 2 2 2 1 4 7 2 3 1 -1 -2 1 0 0 2 1 2 0 1 -1A 100 10 2 7 5 2 2 2 1 4 7 2 3 1 -1 -2 1 0 0 2 1 2 0 1 77 13 2 6 4 2 2 2 1 4 6 2 3 1 -1 -2 1 0 0 2 1 2 0 1 Notes 1 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Notes: 1. IRCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Block Diagram
CLK CKE
Clock Generator Bank 3 Bank 2 Bank 1 Row Address Buffer & Refresh Counter
Address
Mode Register
Row Decoder
Bank 0
Sense Amplifier
Command Decoder Control Logic
/CS /RAS /CAS /WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Pin Function
CLK (input pin) CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE (input pins) CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends operation. When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS (input pins) /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 to A11 (input pins) Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. Column Address is determined by A0 to 7 at the CLK rising edge in the read or write command cycle. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. BA0 and BA1 (input pin) BA0 and BA1 are bank select signal. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. DQM (input pins) DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 to DQ31 (input/output pins) DQ pins have the same function as I/O pins on a conventional DRAM. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE) The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through A11 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this command, the Synchronous DRAM cannot accept any other commands.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add
Mode Register Set Command Activate command (/CS, /RAS = Low, /CAS, /WE = High) The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add
Row Row
Row Address Strobe and Bank Activate Command
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Precharge command (/CS, /RAS, /WE = Low, /CAS = High) This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the Synchronous DRAM can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's /RAS rising.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10
(Precharge select)
Add
Precharge Command Write command (/CS, /CAS, /WE = Low, /RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add Col.
Column Address and Write Command
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Read command (/CS, /CAS = Low, /RAS, /WE = High) Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add Col.
Column Address and and Read Command CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the Synchronous DRAM cannot accept any other command
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add
CBR (auto) Refresh Command
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
A10 Add
Self Refresh Entry Command Burst stop command (/CS = /WE = Low, /RAS, /CAS = High) This command can stop the current burst operation.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add
Burst Stop Command in Full Page Mode No operation (/CS = Low, /RAS, /CAS, /WE = High) This command is not an execution command. No operations begin or terminate by this command.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add
No Operation
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Truth Table
Command Truth Table
CKE Function Device deselect No operation Burst stop Read Read with auto precharge Write Write with auto precharge Bank activate Precharge select bank Precharge all banks Mode register set Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL MRS n-1 H H H H H H H H H H H n x x x x x x x x x x x /CS H L L L L L L L L L L /RAS x H H H H H H L L L L /CAS x H H L L L L H H H L /WE x H L H H L L H L L L BA0, BA1 x x x V V V V V V x L A10 x x x L H L H V L H L A9 - A0, A11 x x x V V V V V x x V
Remark: H: VIH. L: VIL. x: VIH or VIL, V = Valid data DQM Truth Table
CKE Function Data write / output enable Data mask / output disable DQ0 to DQ7 write enable/output enable DQ8 to DQ15 write enable/output enable DQ16 to DQ23 write enable/output enable DQ24 to DQ31 write enable/output enable DQ0 to DQ7 write inhibit/output disable DQ8 to DQ15 write inhibit/output disable DQ16 to DQ23 write inhibit/output disable DQ24 to DQ31 write inhibit/output disable Symbol ENB MASK ENB0 ENB1 ENB2 ENB3 MASK0 MASK 1 MASK 2 MASK 3 n-1 H H H H H H H H H H n x x x x x x x x x x DQM 0 L H L x x x H x x x 1 L H x L x x x H x x 2 L H x x L x x x H x 3 L H x x x L x x x H
Remark: H: VIH. L: VIL. x: VIH or VIL
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
CKE Truth Table
CKE Current state Activating Any Clock suspend Idle Idle Self refresh Function Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR (auto) refresh command Self refresh entry Self refresh exit REF SELF Symbol n-1 H L L H H L L Idle Power down entry H H Power down Power down exit L L n L L H H L H H L L H H /CS x x x L L L H L H H L /RAS x x x L L H x H x x H /CAS x x x L L H x H x x H /WE x x x H H H x H x x H Address x x x x x x x x x x x
Remark: H: VIH. L: VIL. x: VIH or VIL
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Function Truth Table*
Current state Idle /CS H L L L L L L L Row active H L L L L L L L Read H L L L L L L L L Write H L L L L L L L L
1
/RAS /CAS /WE Address x H H H L L L L x H H H L L L L x H H H H L L L L x H H H H L L L L x H L L H H L L x H L L H H L L x H H L L H H L L x H H L L H H L L x x H L H L H L x x H L H L H L x H L H L H L H L x H L H L H L H L x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE
Command DESL NOP or BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Operation Nop or power down Nop or power down ILLEGAL ILLEGAL Row activating Nop CBR (auto) refresh or self refresh Mode register accessing Nop Nop Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Terminate burst, new read: Determine AP
Notes 2 2 3 3
4
5 5 3 6
7
Terminate burst, begin write: Determine AP 7, 8 ILLEGAL Terminate burst, Precharging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read : Determine AP Terminate burst, new write : Determine AP ILLEGAL Terminate burst, Precharging ILLEGAL ILLEGAL 7, 8 7 3 9 3
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Current state Read with auto precharge
/CS H L L L L L L L L
/RAS /CAS /WE Address x H H H H L L L L x x H H L L H H L L x x H L H L H L H L x x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE
Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL
Operation Continue burst to end Precharging Continue burst to end Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Write recovering with auto precharge Continue burst to end Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP Nop Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter bank active after tRCD Nop Enter bank active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
3 3 3 3
Write with auto precharge
H
L L L L L L L L Precharging H L L L L L L L L Row activating H L L L L L L L L
H H H H L L L L x H H H H L L L L x H H H H L L L L
H H L L H H L L x H H L L H H L L x H H L L H H L L
H L H L H L H L x H L H L H L H L x H L H L H L H L
NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
3 3 3 3
3 3 3
3 3 3, 10 3
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Current state Write recovering
/CS H L L L L L L L L
/RAS /CAS /WE Address x H H H H L L L L x H H H H L L L L x H H H H x H H H L x H H L L H H L L x H H L L H H L L x H H L L x H H L L x H L H L H L H L x H L H L H L H L x H L H L x H L H L x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OPCODE x x x x x x x x x x
Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/READA
Operation Nop Enter row active after tDPL Nop Enter row active after tDPL Nop Enter row active after tDPL Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter precharge after tDPL Nop Enter precharge after tDPL Nop Enter row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC Nop Enter idle after tRC ILLEGAL
Notes
8
3 3
Write recovering with auto precharge
H L L L L L L L L
3, 8 3 3
Refresh
H L L L L
ACT/PRE/PALL ILLEGAL REF/SELF/MRS ILLEGAL DESL NOP BST READ/READA Nop Enter idle after tRSC Nop Enter idle after tRSC ILLEGAL ILLEGAL
Mode register accessing
H L L L L
ACT/PRE/PLL/ ILLEGAL REF/SELF/MRS
Remark: H: VIH. L: VIL. x: VIH or VIL, V = Valid data BA: Bank Address, CA: Column Address, RA: Row Address Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down mode. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus trun around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Command Truth Table for CKE
CKE Current State Self refresh n-1 n H L L L L L Self refresh recovery H H H H H H H H Power down H L L L All banks idle H H H H H H H H H H L L Row active H L Any state other than listed above H H L L x H H H H L H H H H L L L L x H H L H H H H H L L L L L H L x x H L H L /CS x H L L L x H L L L H L L L x H L x H L L L L H L L L L x x x x x x x x /RAS /CAS /WE Address x x H H L x x H H L x H H L x x H x x H L L L x H L L L x x x x x x x x x x H L x x x H L x x H L x x x H x x x H L L x x H L L x x x x x x x x x x x x x x x x x x x x x x x x H x x x x H L x x x H L x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Operation INVALID, CLK (n - 1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Continue self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK (n - 1) would exit power down EXIT power down EXIT power down Continue power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table CBR (auto) Refresh Notes
OPCODE Refer to operations in Function Truth Table Begin power down next cycle Refer to operations in Function Truth Table Refer to operations in Function Truth Table Self refresh 1
OPCODE Refer to operations in Function Truth Table Exit power down next cycle Power down Refer to operations in Function Truth Table Clock suspend Refer to operations in Function Truth Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend 2 1 1
Remark: H = VIH, L = VIL, x = VIH or VIL Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. Must be legal command as defined in Function Truth Table.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Simplified State Diagram
Self Refresh
LF SE
t exi LF SE
Mode Register Set
MRS IDLE
REF
CBR(auto) Refresh
CK
ACT
E
CK
E
Power Down
CKE ROW ACTIVE
BS T
ite wit pre h ch arg e
CKE
Re ad BS T
Active Power Down
Write
rit W
e
h wit ad arge Re ch pre to Au PRE
Read
Wr
WRITE SUSPEND
CKE WRITE CKE
Au
to
Read
CKE READ CKE
Write
READ SUSPEND
PR E( Pre cha rge ter min atio n)
WRITEA SUSPEND
CKE WRITEA CKE
CKE READA CKE
n) atio min ter rge cha Pre E( PR
READA SUSPEND
POWER ON
Precharge
Precharge
Automatic sequence Manual input
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Programming Mode Registers
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0 and BA1 as data inputs. The registers retain data until it is re-programmed, or the device loses power. The mode register has three fields; Options /CAS latency Wrap type Burst length : : : : A11 through A7, BA0, BA1 A6 through A4 A3 A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. "Relationship between Frequency and Latency" shows the relationship of /CAS latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. "Burst Length Sequence" shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Mode Register
BA0 BA1 A11 0 0 0 A10 0 A10 x A10 A9 0 A9 1 A9 A8 0 A8 0 A8 1 BA0 BA1 A11 x x x A10 x A10 0 A9 x A9 0 A8 1 A8 0 A7 1 A7 0 A7 0 A7 1 A7 0 A6 V A6 A5 V A5 LTMODE A4 V A4 A3 V A3 WT A2 V A2 A1 V A1 BL A0 V A0 Mode Register Set Vender Specific V = Valid x = Don't care A6 A6 A5 LTMODE A5 A4 A4 A3 WT A3 A2 A2 A1 BL A1 A0 Use in future A0 Burst Read and Single Write (for Write Through Cache) A6 A5 A4 A3 A2 A1 A0 JEDEC Standard Test Set (refresh counter test)
BA0 BA1 A11 x x x
BA0 BA1 A11
BA0 BA1 A11 0 0 0
Burst length
Bits2-0 000 001 010 011 100 101 110 111 0 1
WT = 0 1 2 4 8 R R R Full page
WT = 1 1 2 4 8 R R R R
Wrap type
Sequential Interleave
Latency mode
Bits6-4 000 001 010 011 100 101 110 111
/CAS latency R R 2 3 R R R R
Remark R : Reserved
Mode Register Set Timing
CLK CKE /CS /RAS /CAS /WE A0 - A11, BA0(13), BA1(A12) Mode Register Set
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Burst Length and Sequence [Burst of Two]
Starting address (column address A0, binary) 0 1 Sequential addressing sequence (decimal) 0, 1 1, 0 Interleave addressing sequence (decimal) 0, 1 1, 0
[Burst of Four]
Starting address (column address A1 to A0, binary) 00 01 10 11 Sequential addressing sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave addressing sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
[Burst of Eight]
Starting address (column address A2 to A0, binary) 000 001 010 011 100 101 110 111 Sequential addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Address Bits of Bank-Select and Precharge
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1 BA0
BA1(A12) BA0(A13)
Result Select Bank A "Activate" command Select Bank B "Activate" command Select Bank C "Activate" command Select Bank D "Activate" command
(Activate command)
0 0 1 1
0 1 0 1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1 BA0 A10 BA1(A12) BA0(A13) 0 0 0 0 1 0 0 0 1 0 1 1 1 x x x : Don't care Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
(Precharge command)
0 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 x BA1 BA0 1
disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst)
(/CAS strobes)
BA1(A12) BA0(A13)
Result enables Read/Write commands for Bank A enables Read/Write commands for Bank B enables Read/Write commands for Bank C enables Read/Write commands for Bank D
0 0 1 1
0 1 0 1
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Power-up sequence
Power-up sequence The SDRAM should be goes on the following sequence with power up. The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence. The CKE and DQM is driven to high between power stabilizes and the initialization sequence. This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up, the large current flows from these pins to VDD through the diodes. Initialization sequence When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device.
Power up sequence 100 s VDD, VDDQ CKE, DQM CLK /CS, DQ 0V Low Low Low
Power stabilize
Initialization sequence 200 s
Power-up sequence and Initialization sequence
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Operation of the SDRAM
Read/Write Operations Bank active Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register.
CLK
tRCD
Command
ACT READ
Address
Row
Column
DQ
CL = 2 CL = 3
out 0
out 1 out 0
out 2 out 1
out 3 out 2 out 3 CL = /CAS latency Burst Length = 4
/CAS Latency
CLK
tRCD
Command Address
ACT READ
Row
Column
BL = 1
out 0 out 0 out 1
DQ
BL = 2
out 0 out 1 out 2 out 3
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
BL : Burst Length /CAS Latency = 2
Burst Length
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Write operation Burst write or single write mode is selected by the OPCODE of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations. The write start address is specified by the column address and the bank select address at the write command set cycle.
CLK
tRCD
Command Address
ACT
WRIT
Row
Column
BL = 1
in 0 in 0 in 1 in 1 in 1
in 2 in 2
DQ
BL = 2
in 0 in 3 in 3 in 4 in 5 in 6 in 7
BL = 4
in 0
BL = 8
CL = 2, 3
Burst write 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address and the bank select address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CLK
tRCD
Command
ACT
WRIT
Address DQ
Row
Column
in 0
Single write
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Auto Precharge Read with auto-precharge In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is required before execution of the next command. [Clock cycle time]
/CAS latency 3 2
CLK
Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output
CL=2 Command
ACT lRAS
READA
ACT
DQ
out0
out1
out2
out3
lAPR CL=3 Command ACT lRAS DQ out0 out1 out2 out3 READA ACT
Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge "
lAPR
".
Burst Read (BL = 4) Write with auto-precharge In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is required between the final valid data input and input of next command.
CLK Command
ACT ACT
WRITA
IRAS DQ in0 in1 in2 in3 lDAL Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
Burst Write (BL = 4)
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
CLK Command
ACT ACT
WRITA
IRAS DQ in lDAL Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
Single Write
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command.
CLK Command DQ (CL = 2) DQ (CL = 3)
READ BST High-Z
out
out
out
out
out
out
High-Z
Burst Stop at Read During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command.
CLK Command DQ WRITE in in in in BST
High-Z
Burst Stop at Write
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Command Intervals Read command to Read command interval 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK Command
Address
BS
ACT READ READ
Row
Column A Column B
DQ
Bank0 Active
out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout
CL = 3 BL = 4 Bank 0
READ to READ Command Interval (same ROW address in same bank) 2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK Command
Address
ACT
Row 0
ACT
Row 1
READ READ
Column A Column B
BS
DQ
Bank0 Active Bank3 Bank0 Bank3 Active Read Read out A0 out B0 out B1 out B2 out B3 Bank0 Bank3 Dout Dout
CL = 3 BL = 4
READ to READ Command Interval (different bank)
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Write command to Write command interval 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority.
CLK Command
Address
ACT WRIT WRIT
Row
Column A Column B
BS
DQ
Bank0 Active in A0 in B0 in B1 in B2 in B3
Column =A Column =B Write Write
Burst Write Mode BL = 4 Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank) 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
CLK Command
Address
BS
ACT ACT WRIT WRIT
Row 0
Row 1
Column A Column B
DQ
Bank0 Active
in A0
in B0
in B1
in B2
in B3
Bank3 Bank0 Bank3 Active Write Write
Burst Write Mode BL = 4
WRITE to WRITE Command Interval (different bank)
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Read command to Write command interval 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK Command
CL=2
READ WRIT
DQM
CL=3
in B0 High-Z in B3
DQ (input)
in B1
in B2
DQ (output)
BL = 4 Burst write
READ to WRITE Command Interval (1)
CLK Command
READ WRIT
DQM
CL=2
out
2 clock
out out out out in in in in in in in in
DQ
CL=3
READ to WRITE Command Interval (2) 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed.
CLK Command DQM
DQ (input) DQ (output)
WRIT
READ
in A0 out B0 Column = A Write Column = B Read out B1 out B2 out B3
Burst Write Mode CL = 2 BL = 4 Bank 0
/CAS Latency Column = B Dout
WRITE to READ Command Interval (1)
CLK Command DQM DQ (input) DQ (output) Column = A Write Column = B Read in A0 in A1 out B0 out B1 out B2 out B3 Burst Write Mode CL = 2 BL = 4 Bank 0 WRIT READ
/CAS Latency Column = B Dout
WRITE to READ Command Interval (2) 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK Command BS DQ bank0 Read A bank3 Read ". out A0 out A1 out B0 out B1 CL= 3 BL = 4 READA READ
Note: Internal auto-precharge starts at the timing indicated by "
Read with Auto Precharge to Read Command Interval (Different bank) 2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts 2 clocks later from the second command.
CLK Command BS DQ in A0 bank0 Write A in A1 in B0 bank3 Write ". in B1 in B2 in B3 BL= 4 WRITA WRIT
Note: Internal auto-precharge starts at the timing indicated by "
Write with Auto Precharge to Write Command Interval (Different bank) 2. Same bank: The consecutive write command (the same bank) is illegal.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.
CLK Command BS CL = 2 DQM CL = 3 in B0 in B1 in B2 in B3 READA WRIT
DQ (input) DQ (output) bank0 ReadA
High-Z bank3 Write ". BL = 4
Note: Internal auto-precharge starts at the timing indicated by "
Read with Auto Precharge to Write Command Interval (Different bank) 2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command. Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
CLK Command BS DQM DQ (input) DQ (output) bank0 WriteA bank3 Read ". in A0 out B0 out B1 out B2 out B3 CL = 3 BL = 4 WRITA READ
Note: Internal auto-precharge starts at the timing indicated by "
Write with Auto Precharge to Read Command Interval (Different bank) 2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Read command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution.
CLK
Command
READ
PRE/PALL
DQ
out A0
out A1
out A2
out A3
CL=2
lEP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
READ
PRE/PALL
DQ
out A0
out A1
out A2
out A3
CL=3
lEP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
Command
READ
PRE/PALL
High-Z DQ out A0
lHZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
Command
READ
PRE/PALL
High-Z DQ out A0
lHZP =3
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Preliminary Data Sheet E0247E40 (Ver. 4.0)
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EDS1232CABB, EDS1232CATA
Write command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK Command WRIT
PRE/PALL
DQM
DQ
tDPL
CLK Command DQM WRIT
PRE/PALL
DQ
in A0
in A1
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK Command DQM WRIT
PRE/PALL
DQ
in A0
in A1
in A2
in A3
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
Preliminary Data Sheet E0247E40 (Ver. 4.0)
40
EDS1232CABB, EDS1232CATA
Bank active command interval 1. Same bank: The interval between the two bank active commands must be no less than tRC. 2. In the case of different bank active commands: The interval between the two bank active commands must be no less than tRRD.
CLK Command ACT ACT
Address
ROW
ROW
BS
tRC
Bank 0 Active Bank 0 Active
Bank Active to Bank Active for Same Bank
CLK Command Address ACT ROW:0 ACT ROW:1
BS tRRD Bank 0 Active Bank 3 Active
Bank Active to Bank Active for Different Bank Mode register set to Bank active command interval The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK Command MRS ACT
Address
OPCODE
BS & ROW
IMRD Mode Register Set Bank Active
Mode register set to Bank active command interval
Preliminary Data Sheet E0247E40 (Ver. 4.0)
41
EDS1232CABB, EDS1232CATA
DQM Control The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM/LDQM is different during reading and writing. Reading When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks. Writing Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0 clock.
CLK DQM DQ High-Z out 0 out 1 out 3
lDOD = 2 Latency
Reading
CLK DQM
DQ
in 0
in 1
in 3
lDID = 0 Latency
Writing
Preliminary Data Sheet E0247E40 (Ver. 4.0)
42
EDS1232CABB, EDS1232CATA
Refresh Auto-refresh All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below. 1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode. Note: tREF (max.) / refresh cycles. Others Power-down mode The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock suspend mode By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Preliminary Data Sheet E0247E40 (Ver. 4.0)
43
EDS1232CABB, EDS1232CATA
Timing Waveforms
Read Cycle
tCK tCH t CL
CLK
t RC VIH
CKE
tRCD tSI tHI tSI tHI
tRAS tSI tHI
t RP tSI tHI
/CS
tSI tHI tSI tHI tSI tHI tSI tHI
/RAS
tSI tHI tSI tHI tSI tHI tSI tHI
/CAS
tSI tHI tSI tHI tSI tHI tSI tHI
/WE
tSI tHI tSI tHI tSI tHI tSI tHI
BS
tSI tHI tSI tHI tSI tHI tSI tHI
A10
tSI tHI tSI tHI tSI tHI
Address
tSI tHI
DQM
DQ (input)
tAC tAC tAC tHZ
DQ (output)
t AC tOH
Bank 0 Active Bank 0 Read
tOH
tOH
Bank 0 Precharge
tOH
tLZ
/CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL
Preliminary Data Sheet E0247E40 (Ver. 4.0)
44
EDS1232CABB, EDS1232CATA
Write Cycle
tCK tCH tCL
CLK
tRC
VIH
CKE
tRCD tSI tHI tSI tHI tSI tHI tSI tHI tRAS tRP
/CS
tSI tHI tSI tHI tSI tHI tSI tHI
/RAS
tSI tHI tSI tHI tSI tHI tSI tHI
/CAS
tSI tHI tSI tHI tSI tHI tSI tHI
/WE
tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI
BS
tSI tHI
A10
tSI tHI tSI tHI tSI tHI
Address
tSI tHI
DQM
tSI t HI tSI tHI tSI tHI tSI tHI
DQ (input)
tDPL
DQ (output)
Bank 0 Active Bank 0 Write Bank 0 Precharge
CL = 2 BL = 4 Bank 0 access = VIH or VIL
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
lRP
Precharge If needed Mode register Set
VIL
valid
code
R: b
C: b
C: b'
b High-Z lMRD
Bank 3 Active
b+3
b'
b'+1
b'+2
b'+3
lRCD
Bank 3 Read
Output mask
lRCD = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Preliminary Data Sheet E0247E40 (Ver. 4.0)
45
EDS1232CABB, EDS1232CATA
Read Cycle/Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Bank 0 Active Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VIH
Read cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
R:a
C:a
R:b a
C:b a+1 a+2 a+3
Bank 3 Bank 0 Read Precharge
C:b' b
High-Z
Bank 3 Read
C:b" b'+1 b" b"+1 b"+2 b"+3
Bank 3 Precharge
b+1 b+2 b+3 b'
Bank 3 Read
CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
VIH
Write cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
R:a
C:a
R:b
C:b
High-Z
C:b'
C:b"
a
Bank 0 Active Bank 0 Write
a+1 a+2 a+3
Bank 3 Active
b
Bank 3 Write
b+1 b+2 b+3 b'
Bank 0 Precharge Bank 3 Write
b'+1 b"
Bank 3 Write
b"+1 b"+2 b"+3
Bank 3 Precharge
Preliminary Data Sheet E0247E40 (Ver. 4.0)
46
EDS1232CABB, EDS1232CATA
Read/Single Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
Bank 0 Active Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VIH
R:a
C:a
R:b
C:a' C:a a a a+1 a+2 a+3
Bank 0 Bank 0 Read Write
a
a+1 a+2 a+3
Bank 0 Precharge Bank 3 Precharge
CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
VIH
R:a
C:a
R:b
C:a a a a+1 a+3
Bank 0 Write
C:b C:c b c
Bank 0 Active
Bank 0 Read
Bank 3 Active
Bank 0 Bank 0 Write Write
Bank 0 Precharge
Read/Single write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Preliminary Data Sheet E0247E40 (Ver. 4.0)
47
EDS1232CABB, EDS1232CATA
Read/Burst Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
Bank 0 Active Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a' a a a+1 a+2 a+3
Clock suspend
a+1 a+2 a+3
Bank 0 Precharge Bank 3 Precharge
Bank 0 Write
CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
VIH
R:a
C:a
R:b
C:a a a a+1 a+3
Bank 0 Write Bank 0 Precharge
a+1 a+2 a+3
Bank 0 Active
Bank 0 Read
Bank 3 Active
Read/Burst write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
High-Z a a+1
A10=1
VIH
R:a
C:a
t RP
Precharge If needed Auto Refresh
t RC
Auto Refresh
t RC
Active Bank 0 Read Bank 0
Refresh cycle and Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
Preliminary Data Sheet E0247E40 (Ver. 4.0)
48
EDS1232CABB, EDS1232CATA
Self Refresh Cycle
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
t RP
Precharge command If needed Self refresh entry command
A10=1
lSREX
CKE Low
High-Z
t RC
Self refresh exit ignore command or No operation Next clock enable Self refresh entry command
t RC
Auto Next clock refresh enable
Self refresh cycle /RAS-/CAS delay = 3 CL = 3 BL = 4 = VIH or VIL
Clock Suspend Mode
tSI tHI tSI
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input) R:a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
C:a
R:b a a+1 a+2
High-Z
C:b a+3 b b+1 b+2 b+3
Bank0 Active clock Active suspend start
Active clock Bank0 suspend end Read
Bank3 Active
Read suspend start
Read suspend end
Bank3 Read
Bank0 Precharge
Earliest Bank3 Precharge
CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Bank0 Active
Active clock suspend start
Write cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
R:a
C:a R:b
High-Z
C:b
a
a+1 a+2
Write suspend start
a+3 b
Write suspend end
b+1 b+2 b+3
Earliest Bank3 Precharge
Active clock Bank0 Bank3 supend end Write Active
Bank3 Bank0 Write Precharge
Preliminary Data Sheet E0247E40 (Ver. 4.0)
49
EDS1232CABB, EDS1232CATA
Power Down Mode
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output) tRP
Precharge command If needed Power down entry Power down mode exit Active Bank 0
A10=1
CKE Low
R: a
High-Z
Power down cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Initialization Sequence
0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55
CLK CKE /CS /RAS /CAS /WE Address DQM DQ
tRP All banks Precharge Auto Refresh t RC Auto Refresh VIH High-Z tRC l MRD Mode register Set Bank active If needed valid code Valid VIH
Preliminary Data Sheet E0247E40 (Ver. 4.0)
50
EDS1232CABB, EDS1232CATA
Package Drawing
90-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
0.2 S A
8.0 0.1
0.2 S B
13.0 0.1 INDEX AREA
0.2 S
1.07 max.
S
0.27 0.05
0.1 S B
A
INDEX MARK
0.8
0.8 1.6 90-0.45 0.05
0.8
0.9
0.08 M S A B
ECA-TS2-0061-01
Preliminary Data Sheet E0247E40 (Ver. 4.0)
51
EDS1232CABB, EDS1232CATA
86-pin TSOP (II)
Unit: mm
22.22 0.10 86 A
*1
44
PIN#1 ID
1 0.50 0.15 to 0.30 0.81 max.
43
B
0.10 M S A B
11.76 0.20
10.16
0.80 Nom 0 to 8
0.25
1.0 0.05
1.2 max.
0.10 S
0.10 +0.08 -0.05
S
0.09 to 0.20
0.60 0.15
Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side.
ECA-TS2-0030-01
Preliminary Data Sheet E0247E40 (Ver. 4.0)
52
EDS1232CABB, EDS1232CATA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS1232CA. Type of Surface Mount Device EDS1232CABB: 90-ball FBGA < Lead free (Sn-Ag-Cu) > EDS1232CATA: 86-pin TSOP (II)
Preliminary Data Sheet E0247E40 (Ver. 4.0)
53
EDS1232CABB, EDS1232CATA
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0247E40 (Ver. 4.0)
54
EDS1232CABB, EDS1232CATA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0247E40 (Ver. 4.0)
55

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